All x86 CPUs have an instruction called “HLT” (“Halt”), where the CPU remains “stopped”, idle, doing nothing when it is ran. The CPU is put back to life after it receives an interruption, which is a hardware signal that tells the CPU to stop what it is doing at the moment and take care of the hardware device that sent that signal.

Since in halt mode the CPU is completely idle, Intel decided that this would be the perfect place to reduce the CPU power consumption, so they added the “Halt” or “Auto Halt” mode – now known as the C1 state – starting on the 486DX4 processor. All CPUs after 486DX4 from both Intel and AMD implement this mode, and also the “SL Enhanced” version of 486DX2.

So after the program runs an HLT instruction, the CPU enters its traditional halt mode but now the internal CPU clock signal is stopped (only two units inside the CPU continue to be fed with the CPU internal clock, the bus interface unit and the Advanced Programmable Interrupt Controller, APIC; this is done to allow the CPU to temporarily exit the Halt state if an important request comes thru the CPU external bus). As soon as the CPU receives an interruption signal it goes back to its normal operating state, with the clock signal being restored.

Since the clock signal is stopped for almost all CPU internal units, they stop running, making them to consume less power.

Interesting enough no special programming is required for the CPU to enter the C1 state, as HLT instruction is present since the first 8086 CPU. Before the 486DX4 the HLT instruction was used basically to stop the CPU and make it wait for an interruption. After this CPU, programmers could use this mode to put the CPU into a lower power consumption state.

As mentioned, the CPU can temporarily leave the Halt (C1) state to deal with an important request coming from thru the CPU external bus. This temporary leave is called Stop Clock Snoop State, HALT/Grant Snoop State or simply Snoop State and during its duration the CPU clock is restored. After the CPU has handled the request, it goes automatically back to the Halt (C1) state.

All Intel CPUs based on socket 775 (e.g. Pentium 4, Core 2 Duo) have an advanced Halt state called Enhanced Halt (naming used with Pentium 4 CPUs), Extended Halt (naming used with Core 2 Duo CPUs) or simply C1E, which also reduces the CPU voltage besides stopping the CPU internal clock. If this mode is enabled on the motherboard BIOS, the CPU will enter this mode instead of the traditional Halt (C1) mode when a HLT instruction is issue. Otherwise the CPU will continue to use the standard Halt mode.

Core 2 Duo also introduced the Extended Halt/Stop Grant Snoop state, which allows the CPU to temporarily exit C1E or C2E modes to respond to an important request coming from the CPU external bus, but keeping the CPU lower voltage instead of restoring the CPU full voltage.

Pay attention because AMD also uses the name C1E for a completely different thing. On their 65-nm Athlon X2 and Phenom CPUs C1E state works just like the C3 state, shutting down all CPU clocks. The CPU enters C1E state when this option is enabled on BIOS and all CPU cores enter the regular C1 (Halt) state. When this happens, the automatically CPU switches to this C1E state in order to save energy. The difference between AMD’s C1E and C3 states is basically how the CPU enters the Sleep state: while on the traditional C3 state the CPU must be put in that state usually by a command from the operating system, on C1E the CPU enters the Sleep state automatically when all cores are at Halt (C1) state.